***pre-launched with 5 videos***
RISC-V is a free and open RISC instruction set architecture. and was originally developed in Computer Science division of the EECS Department at the University of California, Berkeley
This course will talk a lot about RISC-V ISA from scratch, also including a section about why do we even need a computer architecture and how real-time day-to-day apps run on a computer, with examples
The final aim of this course is to help everyone to build a robust specifications, which is the very first criteria behind system design. In the upcoming courses,, these specifications will be coded in RTL hardware description language using verilog/vhdl and finally the RTL will placed and routed using opensource EDA tool chain.
This course will walk you through the specifications, starting from signed/unsigned integer representation till RV64IMFD Instruction set with some really cool images and examples. The conventions like “IMFD” will also be explored in a unique fashion, which is being never done before and any micro-processor or micro-controller related courses
Acknoledgements –
I would like to Thank SiFive, a company that was founded by the creators of RISC-V ISA.
I would also like to Thank Prof. David Patterson and his book “Computer Organization And Design – RISCV edition” which immensely helped in the making of this course.
Let’s get inside computers…
